1. Field of the Invention
The present invention relates to static random access memories (SRAMs) and, more particularly, to SRAMs which have improved levels of reliability.
2. Description of the Related Art
Reduced geometry integrated circuit designs are adopted to increase the density of devices within integrated circuits, thereby increasing performance and decreasing the cost of the integrated circuits. Modern integrated circuit memories, including DRAMs, SRAMs, ROMs, EEPROMS, etc., are prominent examples of the application of this strategy. The density of memory cells within integrated circuit memories continues to increase, accompanied by a corresponding drop in the cost per bit of storage within such devices. Increases in density are accomplished by forming smaller structures within devices and by reducing the separation between devices or between the structures that make up the devices. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced device sizes or are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many conventional integrated circuits are made possible by improvements in design, such as reduced gate oxide thicknesses and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
Making static random access memories (SRAMs) in accordance with smaller design rules, as well as using reduced internal operating voltages, can reduce the immunity of SRAMs to alpha-particle generated soft errors, thereby reducing the reliability of the SRAMS. Most SRAM designs include four or six MOS transistors cross-coupled together in a latch configuration, with one of the most basic designs including four transistors connected to form cross-coupled inverters. In such a cross-coupled inverter design, the coupled gates of each inverter, along with the diffusion regions directly connected to those gates, form a charge storage node for the memory cell. Thus, there are two charge storage nodes within each SRAM memory cell. Typically, the cross-coupled inverters form a latch having two stable states: one state with a predefined level of charge stored on a first charge storage node and no charge stored on a second charge storage node; and a second state with no charge stored on the first charge storage node and the predefined level of charge stored on the second charge storage node. Binary data is recorded by toggling between the two states of the latch. Sufficient charge must be stored on the charge storage node, and thus on the coupled gates of associated inverter, to unambiguously hold one of the inverters "ON" and the other of the inverters "OFF", thereby preserving the memory state. This memory state is conventionally read out using a differential sense amplifier, so it is the difference in charge levels stored on the two charge storage nodes which must be maintained above a desired level to preserve the performance of the SRAM.
Reduced design rules in SRAMS reduce the size of the transistor gates and of the connected diffusion regions, thereby reducing the capacitance of the charge storage nodes. By reducing the capacitance of the nodes or by reducing the voltage at which charge is stored on the nodes, conventional SRAM designs store reduced levels of charge on the nodes. Reducing the amount of charge stored on the nodes of an SRAM makes it more likely that an undesired charge generation event in the SRAM in the substrate adjacent one of the storage nodes, such as might be associated with alpha particles, can reduce the difference in the charge levels stored on the nodes of the SRAM memory cell to an unacceptably small level and increase the likelihood that an erroneous binary data state will be detected when reading data from the SRAM memory cell.